Module with integrated active substrate and passive substrate

ABSTRACT

Systems and methods are disclosed for a device having one or more active substrates comprising substantially transistors or diodes formed thereon; one of more passive substrate comprising substantially inductors, capacitors or resistors formed thereon; a plurality of bonding pads positioned on the active and passive substrates; and bonding wires connected to the bonding pads.

BACKGROUND

This invention relates generally to a method and apparatus forfabricating an electronic module.

A typical integrated circuit (IC) or semiconductor die includes externalconnection points termed “bond pads” that are in electricalcommunication with integrated circuits formed in or on the activesurface of the die. The bond pads are used to provide electricalconnection between the integrated circuits and external devices, such aslead frames or printed circuit boards. The bond pads also provide sitesfor electrical testing of the die, typically by contact with probes,which send and receive signals to and from the die to evaluate thefunctionality of the die.

In a conventional die/lead frame assembly, the semiconductor die isattached to a die paddle of a lead frame using an adhesive or tape. Thebond pads formed on the face of the die are typically electrically andmechanically attached to lead fingers terminating adjacent the peripheryof the die using thin bonding wires of gold, aluminum or other metals oralloys. Other types of lead frames, such as so-called “leads over chip”(LOC) or “leads under chip” (LUC), dispense with the die paddle andsupport the die from portions of the lead fingers themselves.

Wire bonding is typically a process through which some or all of thebond pads formed on the face of the die are connected to the leadfingers or buses of a lead frame by thin bonding wires. The bondingwires comprise the electrical bridge between the bond pads and the leadsof the packaged integrated circuit. A wire bonding apparatus bonds thebonding wires to the bond pads and to the lead fingers, typically usingheat and pressure, as well as ultrasonic vibration in some instances.Following wire bonding, the lead frame and die are typicallyencapsulated in a plastic (particle-filled polymer) or packaged in apreformed ceramic or metal package. After encapsulation, the leadfingers are then trimmed and usually bent to form external leads of acompleted semiconductor package in what is termed a “trim and form”operation.

Another wire bonding application may include chip-on-board (COB), wherethe back-side surface of a bare IC die is directly mounted on thesurface of a substantially rigid printed circuit board (PCB) or othercarrier substrate, and bond pads on the front-side or active surface ofthe bare die are then wire bonded to wire bondable trace pads orterminals on the surface of the PCB to interconnect circuitry in the diewith external circuitry through conductive traces on the PCB. Likewise,wire bondable traces may be formed from a metal film carried on aflexible polyimide or other dielectric film or sheet similar to thoseemployed in so-called TAB (tape automated bonding) lead framestructures. A die may be back-mounted on the flex circuit and the traceswire bonded to bond pads on the surface of the die.

A typical die bond pad is formed as a rectangle or square framed orbounded by a passivation layer on the face of the die. Bond pads aretypically formed from a conductive metal such as aluminum andelectrically connected to an underlying integrated circuit formed in oron the die. A passivation layer formed of a dielectric material (silicondioxide, silicon nitride, polyimide, BPSG, etc.) or as a sandwich ofdifferent materials (e.g., silicon dioxide/silicon) covers the oxidelayer, and the bond pad is embedded in the passivation layer. Such bondpads may be located generally along the peripheral edges of the die,inset from the edges a desired distance, or in one or more center rows.These bond pads are then typically wire bonded to a lead frame,thermocompression bonded to an overlying TAB tape or flip-chip bonded(with appropriate prior “bumping” of the bond pads) to a printed circuitboard.

U.S. Pat. No. 6,630,372 discloses a semiconductor device, such as anintegrated circuit die, that includes a plurality of bond pads on anactive surface thereof electrically connected to internal circuitry ofthe semiconductor device, and a plurality of jumper pads on the activesurface, which are electrically isolated from internal circuitry of thedie. The jumper pads effectively provide connection for wire bonds to bemade across the active surface between bond pads. The jumper pads may beformed directly on the semiconductor device or on a non-conductivesupport structure that is attached to the semiconductor device. The '372patent notes that it is often desirable to interconnect various bondpads on a single semiconductor die in order to alter the input and/oroutput functionality of the die, such as when it is necessary to “wirearound” defective portions of a die which is only partially functional.For example, a 16 megabit DRAM memory die may only demonstrate 11megabits of functional memory under electrical testing and burn-in.Alternatively, it may be desirable for a die having a given input/output(bond pad) configuration to “look” to a particular lead frame or carriersubstrate as if it were configured differently so that the die could beused with a lead frame for which it was not originally intended.

The device of the '372 patent shows embodiments of radio frequency (RF)circuits used in wireless communications. The RF circuit typicallyconsists of transistors, diodes, and a large network of passivecomponents such as inductors (L), capacitors (C) and resistors (R). Dueto the physics of inductor and capacitor, these networks of passivecomponents often takes up large die area. To reduce the die cost, RFmodule are commonly made of IC and discrete passive elements which areSMD mounted on a multi-layer printed circuit board (PCB) substrate orembedded in a ceramic structure such as low-temperature co-firedceramics (LTCC) substrate. However, modules made with discretecomponents are generally bulky limiting the ability to reduce modulesize. Further, imprecise control of substrate material property,dimension, or circuit layout often results in low RF performance.

SUMMARY

Systems and methods are disclosed for a device having an activesubstrate comprising substantially transistors or diodes formed thereon;a passive substrate comprising substantially inductors, capacitors orresistors formed thereon; a plurality of bonding pads positioned on theactive and passive substrates; and bonding wires connected to thebonding pads.

Implementations of the device may include one or more of the following.The module can be made of one or more active substrates for active andcertain supporting passive components. The module can include one ormore substantially passive substrates for passive components only. Thesubstrates are interconnected with bonding wires. The substrates can bemounted on a metal lead-frame, and can be encapsulated in moldedplastics. The active substrate contains primarily for transistors, whichcould be either Silicon Biploar, CMOS, RFCMOS, BICOMS, SiGe, GaAs HBT,HEMT, etc. They are typically made from more expensive wafers with thesemiconductor layer structure, with active devices, junctions, anddopings. The passive substrate is for circuits network of R, L, C whichdo not need active device structure. A few conductive metal layers canbe used on the passive substrate for inductor (L) and interconnection.An insulating layer with suitable dielectric properties such as Nitrideor Oxide can be used as the dielectric layer for capacitor (C). Thepassive substrate can include a layer such as TaN and NiCr for resistor(R). Passive components can still be on the die of the active IC, butthe bulky elements of circuit of passive components such as transmissionlines, impedance matching network, filters, balun, or diplexers arelocated in the inexpensive dies of passive substrate.

Advantages of the module can include one or more of the following. Thepassive substrates are manufactured on semi-insulating GaAs or insulatorwafer without the active transistor structure layer, which reduce wafercost and processing time. Passive components on the passive substratesare made with precision semiconductor process with high quality controlof component values. Comparing with PCB, the higher dielectric constantof GaAs results in smaller size for same RF circuit. The metal leadframe provides better heat dissipation for power devices. RF modules canbe made with metal lead frame, thus eliminating PCB/LTCC substrate andSMD steps. The metal lead frame also allows higher temperature insubsequent manufacturing steps.

BRIEF DESCRIPTION OF THE DRAWINGS

In order that the manner in which the above recited and other advantagesand features of the invention are obtained, a more particulardescription of the invention briefly described above will be rendered byreference to specific embodiments thereof, which are illustrated, in theappended drawings. Understanding that these drawings depict only typicalembodiments of the invention and are not therefore to be considered tobe limiting of its scope, the invention will be described and explainedwith additional specificity and detail through the use of theaccompanying drawings in which:

The accompanying drawings, which are incorporated in and form a part ofthis specification, illustrate embodiments of the invention and,together with the description, serve to explain the principles of theinvention:

FIG. 1 is a system diagram of a module having active and passivesubstrates on the die pad.

FIG. 2 is the electrical schematics for a wireless module in accordanceto an embodiment of the present invention.

FIG. 3 illustrates an exemplary IC pin-out.

DESCRIPTION

Reference will now be made in detail to the preferred embodiments of theinvention, examples of which are illustrated in the accompanyingdrawings. While the invention will be described in conjunction with thepreferred embodiments, it will be understood that they are not intendedto limit the invention to these embodiments. On the contrary, theinvention is intended to cover alternatives, modifications andequivalents, which may be included within the spirit and scope of theinvention as defined by the appended claims. Furthermore, in thefollowing detailed description of the present invention, numerousspecific details are set forth in order to provide a thoroughunderstanding of the present invention. However, it will be obvious toone of ordinary skill in the art that the present invention may bepracticed without these specific details. In other instances, well knownmethods, procedures, components, and circuits have not been described indetail as not to unnecessarily obscure aspects of the present invention.

FIG. 1 shows an exemplary semiconductor device 10. The device 10 can beany suitable communications circuit. The device 10 of FIG. 1 ismanufactured to deliver excellent RF, analog, and digital performanceand reliability at a competitive cost. This is achieved by separatingthe circuit into one or more active substrates that are electricallyconnected to one or more passive substrates, all of which are positionedon a die pad for subsequent soldering onto a communications printedcircuit board.

As illustrated in FIG. 1, the module 10 is a device, which includes adie pad 12 of generally rectangular configuration. The module has asurface carrying a plurality of conductive pads called pins 16 proximateits perimeter. The pins 16 and the die pad 12 are packaged as anintegral part of the module 10, making contact with and providing anexternal contact for internal circuitry (not shown) contained within themodule 10. The pins 16 and the die pad 12 can be encapsulated ininsulating material such as plastics or ceramics to become an integralpart as is known in the art. The die pad 12 can be used as a ground,providing direct thermal path for heat removal from the module.

The pins 16 are preferably formed from a conductive material such as ametal, metal alloy, or any other suitable material known in the art towhich a wire bond can be attached. The pins 16 may be mechanicallystamped, chemically etched, silk-screened, printed, sprayed through apatterned mesh, electrochemically deposited, or electroplated,electroless-plated or otherwise formed to the preferred pattern.

The integrated circuit dies, which are fabricated on semiconductorsubstrates, are mounted on the die pad 12. A first active substrate 20,a second active substrate 30 and a first passive substrate 40 aremounted on the die pad 12. In one embodiment, the active substrate 20can include power amplifiers and low noise amplifiers, while the secondactive substrate 30 can include switches thereon. The first passivesubstrate 40 includes passive components such as capacitors, inductorsor resistors that form filters and diplexers, among others. Eachsubstrate 20, 30 or 40 contains a number of bonding pads 22 that-areelectrically connected (wire-bonded) to other bonding pads 22 on thesubstrates 20, 30 or 40 or to pins 16 on the die perimeter. Moreover,each substrate 20, 30 and 40 may have intra-substrate pads that allowwire-bonding to be done within a substrate.

The first and second active substrates 20 and 30 can be combined intoone active substrate, or alternatively, can be split into a number ofactive substrates. Further, passive devices can be used in the activesubstrates 20 and 30. However, due to cost and performance reasons, itis preferred that the active substrates 20 and 30 contain mainly activedevices such as diodes and transistors that form the PAs and the LNAs.Similarly, due to cost reasons, the passive substrate 40 contains mostlypassive devices such as capacitors, inductors and resistors even thoughon occasions, the passive substrate 40 can contain a few diodes andtransistors that do not need the precision and performance of devicesfabricated on the active substrates 20 and 30. In one embodiment, thesubstrates can be fabricated using gallium arsenide (GaAs) and inparticular the active substrates can be processed to form heterojunctionbipolar transistors (HBT) thereon. Other semiconductor materials mayalso be used.

The substrates 20, 30 and 40 may be preformed, and each adhesivelyattached to the die surface with an adhesive such as an epoxy or othersimilar material known in the art.

The semiconductor dies 20, 30, and 40 can be mounted to a conventionallead frame as is known in the art. Alternatively, the lead frame caninclude a plurality of lead fingers extending outwardly from proximatethe perimeter of the module 10 and a die paddle which supports the die10 relative to the lead fingers. The lead fingers form leads for apackaged semiconductor device after transfer-molded polymerencapsulation of the dies 20, 30 and 40 and lead frame as is known inthe art.

Wire bonds 32 can then be formed: between bonding pads 22 and pins 16;between inter-chip bond pads, between adjacent or proximate bond pads;between bond pad and intra-chip pad. The termination points of wirebonds 32 can be of ball, wedge, or other configuration as is known inthe art, and formed with a conventional wire bonding machine.Accordingly, a large number of I/O alternative configurations can beachieved for any semiconductor device, depending on the number andlayout of the pads and configuration of wire bonds.

In one embodiment, the active substrates 20 and 30 are gallium arsenidesubstrates. The fabrication of gallium arsenide structures may begin byapplying an organic photoresist layer on the upper surface of a galliumarsenide substrate and patterning it in an appropriate manner to form,for example, a field effect transistor (FET) active layer mask. The nextstep is to ion implant impurities through the photoresist mask wherethere are windows or openings to form a doped region extending from thesurface of the gallium arsenide substrate to a predetermined depth. Thephotoresist layer is subsequently removed and a capping layer isdeposited over the gallium arsenide substrate.

The material of a capping layer may, for example, be silicon nitride,silicon oxide, phosphorus-doped silicon oxide or aluminum nitride. Thepurpose of the capping layer is to reduce the outgassing of arsenic fromthe gallium arsenide substrate when the ion implanted region isannealed. The ion-implanted region is annealed by raising the galliumarsenide substrate to a high temperature such as 800 degrees C. topermit recrystallization of the gallium arsenide damaged by the ionimplantation. During recrystallization, substitution of theion-implanted ions into the crystal lattices of the gallium arsenidematerial occurs. After the ion-implanted region is annealed, a step alsocalled activation, the capping layer is removed and further processingcontinues. This includes the formation of ohmic contacts defining drainand source and deposition of material suitable to form the gate of afield effect transistor. The protective capping layer is appliedsubsequent to the step of ion implantation. After the step of annealing,the capping layer is removed by selective chemical etching. Thefabrication of the active structures such as transistors and diodes onthe active substrates therefore involve many steps.

In the case of GaAs HBT, complicated 3D structures of emitters, basesand collectors must be formed. The processing requires many steps ofmask and photoresist for etching and lift-off of layers. Similarly, manysteps of masks and layers for CMOS, BICMOS, and SiGe semiconductor diesare known to those skilled in the art.

In contrast, the passive substrate 40 involves relatively simplegeometries that define the RLC properties of the respective componentbeing defined. Hence, the fabrication of the passive structures such asresistors, inductors and capacitors on the active substrate 40 involvefewer steps than those for the active substrates 20 and 30. Hence, thestructure of active substrates 20 and 30 are more complicated andexpensive than the passive substrates 40 to fabricate. By separating themanufacturing of passive substrates from the active substrates, over-allyield is improved, thus also reducing cost. Moreover, because thepassive components are formed using semiconductor manufacturingtechniques on gallium arsenide substrates, the electrical property anddimensions of each passive component can be tightly controlled, thusyielding better performance than modules with typical off-chip passivecomponents.

FIG. 2 shows an exemplary circuit that is partitionable into circuits onan active and a passive substrate. In this embodiment is a dual bandfront-end module (FEM) for communications circuitry such as highperformance 802.11 a/b/g wireless LAN circuits. The module can be aunitary device for wireless communications, and can include integratedpower amplifiers (PAs), low noise amplifiers (LNAs), switches and othercircuitry and auxiliary electronic components, for example. In oneembodiment, the module integrates dual band power amplifiers, dual bandlow noise amplifiers, switch, diplexer, baluns, filters, impedancematching networks, bias control, and power sensors to simplify designand production of end products. Bias control and compensation circuitryensures stable performance over wide operating temperature range.

The circuit of FIG. 2 includes a plurality of filters whose outputs arefed to impedance matching circuits. The baluns, filters and matchingcircuits are substantially passive circuits, so these circuits can beplaced on the passive substrate 40 of FIG. 1. Since the PA and LNAcircuits are primarily active, these circuits belong on the activesubstrate 20. The input to the LNA and the output from the PA areprovided to additional sets of match circuits, filters and diplexer,which are again formed on the passive substrate 40 since matchingcircuits, filters and diplexer uses primarily RLC components. Theoutputs of the diplexers are provided to a switch, which in turn isconnected to antennas. Since the switch uses transistors, it belongs onan active substrate. In the embodiment of FIG. 1, the switch isfabricated on a separate active substrate 30 due to space constraints onthe active substrate 20.

FIG. 3 illustrates an exemplary pin-out diagram of an exemplary IC forthe circuit of FIG. 2. The pin-out shows the bottom side of the IC thatincludes a multitude of metal electrodes and an insulating substrate.The IC can include a center ground, which is the exposed bottom side ofdie pad, serving as major path for dissipating heat generated by theactive substrate. To keep the amplifiers running without excessivetemperature, it is important to minimize the heat transfer resistance ofthe active substrate to external space on printed circuit. It is alsodesirable to have minimal electrical resistance for the current flowingbetween the center ground and the ground of the circuit board of thewireless device.

In the typical application for a wireless communication device, the ICof FIG. 3 is electrically mounted to a printed circuit board in thewireless communication device. The circuit board includes a groundingcircuit design at the location where the IC is mounted.

Those skilled in the art will appreciate that semiconductor devicesaccording to the present invention may include an integrated radiofrequency (RF) transceiver circuit. An electronic system includes aninput device and an output device coupled to a processor device which,in turn, is coupled to an RF circuit incorporating the exemplaryintegrated circuit module 10 of FIG. 1.

The module 10 can also be employed for storing or processing digitalinformation, including, for example, a Dynamic Random Access Memory(DRAM) integrated circuit die, a Static Random Access Memory (SRAM)integrated circuit die, a Synchronous Graphics Random Access Memory(SGRAM) integrated circuit die, a Programmable Read-Only Memory (PROM)integrated circuit die, an Electrically Erasable PROM (EEPROM)integrated circuit die, a flash memory die and a microprocessor die, andthat the present invention includes such devices within its scope. Inaddition, it will be understood that the shape, size, and configurationof bond pads, jumper pads, dice, and lead frames may be varied withoutdeparting from the scope of the invention and appended claims. Forexample, the jumper pads may be round, oblong, hemispherical orvariously shaped and sized so long as the jumper pads provide enoughsurface area to accept attachment of one or more wire bonds thereto. Inaddition, the bond pads may be positioned at any location on the activesurface of the die.

Although specific embodiments of the present invention have beenillustrated in the accompanying drawings and described in the foregoingdetailed description, it will be understood that the invention is notlimited to the particular embodiments described herein, but is capableof numerous rearrangements, modifications, and substitutions withoutdeparting from the scope of the invention. Accordingly, the claimsappended hereto are written to encompass all semiconductor devicesincluding those mentioned. Those skilled in the art will also appreciatethat various combinations and obvious modifications of the preferredembodiments may be made without departing from the spirit of thisinvention and the scope of the accompanying claims.

1. A device, comprising: one or more active substrates comprisingsubstantially transistors or diodes formed thereon; one or more passivesubstrates comprising substantially inductors, capacitors or resistorsformed thereon; a plurality of bonding pads positioned on the active andpassive substrates; and bonding wires connected to the bonding pads. 2.The device of claim 1, further comprising a die pad to receive theactive 10 and passive substrates.
 3. The device of claim 2, furthercomprising one or more pins and wherein one or more of the bonding wiresconnect one or more bonding pads to the one or more pins.
 4. The deviceof claim 1, wherein the substrates comprise gallium arsenide substrates.5. The device of claim 1, wherein the active substrate comprisessupporting passive components.
 6. The device of claim 1, furthercomprising a substantially passive IC coupled to the active substrate.7. The device of claim 1, further comprising one or more substantiallypassive ICs for passive components only.
 8. The device of claim 1,wherein the substrates are interconnected with bonding wires.
 9. Thedevice of claim 1, wherein the substrates are mounted on a metal diepad.
 10. The device of claim 1, wherein the substrates are encapsulatedin molded plastics or other insulating medium.
 11. The device of claim1, wherein the active substrates comprises primarily transistors. 12.The device of claim 11, wherein the transistors include silicon bipolar,CMOS, RFCMOS, BICOMS, SiGe, GaAs HBT, or HEMT.
 13. The device of claim11, wherein the transistors are fabricated on a wafer with semiconductorlayer structure, junctions, and dopings.
 14. The device of claim 1,wherein the passive substrate comprises a network of resistor (R),inductor (L), and capacitor (C) without active device structure.
 15. Thedevice of claim 1, wherein the passive substrate comprises one or moreconductive metal layers for inductor (L) and interconnection.
 16. Thedevice of claim 1, wherein the passive substrate comprises an insulatinglayer with suitable dielectric properties.
 17. The device of claim 16,wherein the insulating layer comprises Nitride or Oxide as thedielectric layer for a capacitor (C).
 18. The device of claim 1, whereinthe passive substrate comprises a layer including TaN or NiCr for aresistor (R).
 19. The device of claim 1, wherein the passive substratecomprises one or more circuits of passive components includingtransmission lines, impedance matching network, filters, baluns, ordiplexers.
 20. The device of claim 1, wherein the passive substrate isfabricated using fewer fabrication steps than the active substrate.